- HERON-IO5V-DO has Xilinx Virtex®-II FPGA with 1.5M or 3M gates
Need a larger FPGA? See here.
- FPGA configuration downloaded using the HERON Serial Bus.
- Choice of clocking options
- Two 210MSPS 12 bit A/Ds connected to the FPGA
- Two 160MSPS 16 bit D/As connected to the FPGA
- High analog signal bandwidth of 450Mhz in and 145Mhz out
- 8 uncommitted digital I/Os
- Connects to all of the HERON FIFOs, UMI and module ID signals
- This module can be used with ready made IP to perform often used functions
- Single ended version available
(ex VAT & shipping) HERON-IO5V-1500-DO: £2,250, HERON-IO5V-3000-DO: £3,000
HERON-IO5-DO is supplied with a standard set of cables, included in the hardware price. See the information about the HERON-IO5-DO cable set.
The HERON-IO5 provides a user programmable FPGA along with fast Analog Inputs and outputs for a HERON system. The FPGA controls the sampling of the A/Ds and D/As. The incoming digitised data is then fed to the FPGA where it can be processed, buffered or simply written to a HERON FIFO for use in the rest of the system. The outgoing digitised data is then fed from the FPGA where it can be processed, buffered or simply read from a HERON FIFO.
Using the HERON serial bus allows the FPGA to be configured with a standard module configuration, or a custom one provided by the user or HUNT ENGINEERING. After configuration the module can accept user messages over the HERON serial bus, allowing registers etc to be programmed. If a more significant programming change is required a complete new FPGA configuration can be downloaded. The FLASH based configuration PROM can load the configuration data into the FPGA when it is used in an embedded system This PROM can be programmed using the standard JTAG cable available from Xilinx (such as Xilinx® Parallel cable 4 or USB-JTAG cable).
The Digital I/O has a number of voltage formats such as LVTTL or LVCMOS defined by the configuration downloaded to the FPGA.
The HERON-IO5 can access HERON-FIFOs at a rate of 32 bits per FIFO clock in AND 32 bits per FIFO clock out concurrently. For example with a FIFO clock of 100Mhz this is 400Mbytes/sec in AND 400Mbytes/sec out.
The use of a Virtex®-II XC2V**fg676-6
part allows clock rates of up to 365Mhz, and also provides hard coded
multipliers and extended I/O formats such as Low Voltage Differential Signalling
NOTE: Virtex II I/Os are not 5v tolerant!
|Memory:||None external to FPGA|
|Maximum Dimensions:||4.0 inches x 2.5inches x 6.5mm high.|
|Power requirements:||5V dependent on FPGA
12V Max: 500 mA
Typ: 300 mA
Max Bare FPGA package dissipation: 2.8W
A/Ds Max to 210Mhz
D/As 0hz to 160Mhz
FPGA max: dependent on your FPGA design
|I/O bandwidth:||e.g. HEPC9 400Mb/s in + 400Mb/s out|
|Analog I/P specifications:||Channels
2 with common or independent clocking
Two connectors per channel: ultra-miniature 50 Ohm coaxial Hirose U.FL-R-SMT
Standard input characteristics
A/C coupled 50R signal B/W from 200Hz to 450Mhz
Zero input noise typically 3 levels maximum 8 levels
Input voltage +/-0.768mV
Offset typically +-3 levels maximum +-8 levels
(differential input mode)
Input voltage +/-0.768mV
Optional Input Types
A/C coupled, with 50R on each input to ground as standard, but choose I/P impedance from 50R to 1.7K
D/C coupled choose I/P impedance between differential inputs from 50R to 1.7K, Signal B/W 0hz to 450Mhz but each input must not exceed the range 0v to +5V (of this module). This means a 2.8V DC offset is required.
Zero input noise typically 3 levels maximum 10 levels
Offset typically +-12 levels maximum +-16 levels
|Analog O/P specifications:||
Xilinx Foundation series tools are required to make a new FPGA configuration.
HUNT ENGINEERING provide software to download the FPGA configuration file onto the hardware, plus configuration examples.
HUNT ENGINEERING may offer to provide your configuration file for you, but this may be chargeable.
Need a ready made function? See the IP available for HERON-IO5-DO,
(documents open in new window)