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Transient Analysis and Pattern Generation with the HERON-IO5 Module
- Standard IP to perform high speed capture of data into a buffer internal to the FPGA.
- Standard IP to perform continuous waveform generation from a buffer internal to the FPGA.
- VHDL sources so that you can add your own FPGA design to this interface which uses only a very small proportion of the FPGA resources
When combined with this standard bitstream, the HERON-IO5 provides a 511 sample capture buffer inside the FPGA. Via the Heron Serial Bus, a command can be issued to capture a buffer of between 1 and 511 samples, which will then be made available via the HERON FIFO. The HERON FIFO number to be used is programmed using HSB. Data is digitised by both A/D channels at 100Mhz
This part of this IP is useful for capturing bursts of high speed data, that can be analysed offline by a DSP or Host machine. This makes it ideal for a Transient analysis type application.
For the D/A side this IP provides a 512 sample SRAM buffer for each of the D/A channels. Data will be read from this SRAM at 100Mhz. The SRAM can be written with a pattern at any time using a HERON FIFO. The FIFO number to be used can be programmed via HSB.
This part of this IP is useful for using a DSP or Host computer to calculate off-line, the wave shape that is required. It can be written slowly into the SRAM buffer but will then be replayed in a loop at 100Msps. This makes it ideal for programmable pattern generation applications.
Functional Block Diagram
Full documentation and downloads for this IP are here
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