Data Streaming with the HERON-IO2 Module
- Streaming of one or two channels of A/D over HERON-FIFO at a rate determined by an external clock
- Streaming of one or two channels of D/A over HERON-FIFO at a rate determined by an external clock
- VHDL sources so that you can add your own FPGA design to this interface which uses only a very small proportion of the FPGA resources
When using the Data Streaming IP, the HERON-IO2 clocks the A/Ds using an external clock that is applied to the CLKI2 input of the module. The sample data is continuously written into a FIFO that is internal to the FPGA, and the other end of that FIFO is continuously read, and placed into a HERON-FIFO. The HERON-FIFO number to be used is selected using a Heron Serial Bus (HSB) message This internal buffer allows a temporary storage of the data if the reader is halted for a short time. The use of data from one or two channels of the A/D can be selected via the HSB.
If the sample rate is too high for the rate at which the reader can read, the internal FIFO will become full and data will be lost. In that case the User LED0 is lit, and held alight for 1/10th second to indicate data loss.
This makes the HERON-IO2 perform as a high speed data acquisition module, that uses its internal FIFO to achieve a higher A/D sample rate by buffering data when a reader, for example a DSP, delays reading from the HERON FIFO.
The IP also provides a FIFO in the FPGA to buffer data that is being streamed to the D/As. The D/A output rate is set using an external clock CLKI3. The sample data is continuously read from the internal FIFO at that rate. Data is continuously read from the HERON FIFO into this internal FIFO, while data is available. The HERON FIFO number to be used is set using an HSB message. The use of one or two D/A channels is also set using an HSB message.
If the sample rate is too high for the writer of the data, the internal FIFO will eventually become empty. In that case the user LED1 will be lit for 1/10th second to indicate that samples could not be updated. In that case the DAC repeats the output level from the previous sample.
This makes the HERON-IO2 perform as a high speed data output device, using its internal FIFO as a buffer to store data that may be generated in bursts by a processor such as a host or DSP.
Functional Block Diagram
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