Hardware Interface Layer (HIL) for FPGA modules
Allowing your VHDL to correctly access the system hardware without needing to understand the hardware details. It takes care of the correct signal use and timings "by design" allowing you to concentrate on your application VHDL.
We provide VHDL example projects for each of our FPGA based modules.
Each example consists of a VHDL “top level”, with corresponding user constraints file, VHDL sources for the Hardware Interface Layer, and example user application VHDL files. There are also test benches and stimuli files allowing you to perform functional simulation of the examples.
The Hardware Interface Layer correctly interfaces with the Module hardware, while the top level (top.vhd) defines all inputs and outputs from the FPGA on your module. By providing this we remove the need for you to look up, understand and work out how to use the hardware that is external to the FPGA.
It allows you to access all 12 HERON FIFOs from your VHDL design, offering a choice of ways to use it.
The file user_ap.vhd is where you will make your design for the FPGA, using the simplified interfaces provided by the Hardware Interface layer.
After synthesising your design, you will use the Place and Route tools from Xilinx (either as part of your ISE package, or from the Xilinx Alliance tools). These tools will use the User Constraints File (.ucf) to define the correct pins and timing parameters. You will need to minimally edit this file to have the timing constraints that you need, but the file provided means you do not need to enter the pin out constraints at all.
