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Test SDRAM Memory with the HERON-FPGA12 Module
- Standard IP that you can download to an HERON-FPGA12 module to test all DDR SDRAM locations to check the integrity of the memory
- The test uses a combination of different data patterns that are read and written to all locations of memory.
- VHDL sources so that you can add your own FPGA design to this interface which uses only a small proportion of the FPGA resources
Typically this bitstream will read and write all memory locations with all of the test patterns. This performs a thorough check of the DDR SDRAM.
At the heart of this IP is the Control State Machine which controls how an iteration of the memory test is performed. A single iteration of the memory test involves reading and writing to the DDR memory with one particular test pattern, it is triggered by sending one word over HERON input FIFO 0. For one iteration the memory can be written only, read only or both written and then read. One of six test patterns can be selected for an iteration.
A pre-compiled Windows program is supplied for the host machine. This can be used to communicate with the HERON-FPGA12 to run the standard memory test sequence. This program performs five loops of the test sequence, for each loop the DDR memory is both written and read with each of the six test patterns. Whenever a data error is detected the program displays the error and waits for a key press; if all five loops are completed without error the program displays success and terminates.
Functional Block Diagram
All I/O modules have options for cables and clocks. Please see our Cables &Clocks policy for more details.
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Datasheet
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