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HERON-FPGA12 Module

HERON-FPGA12 Virtex^®-4FX12 FPGA module with 128Mbytes DDR SDRAM, Flash memory and 60 bits Digital I/O

• Xilinx XC4VFX12 Virtex^®-4 FPGA with embedded PowerPC^® 
  Need a larger FPGA? See here.
• 128Mbytes of DDR SDRAM connected as 32Mx32 @ 200Mhz
• 16Mbytes of FLASH memory for PowerPC code storage
• FPGA configuration downloaded using the HERON Serial Bus.
• Choice of clocking options
• 60 bits DIO
• Connects to all of the HERON FIFOs, UMI and module ID signals
• Flash PROM for storage of FPGA configuration data
• This module can be used with ready made IP to perform often used functions

Price: 
(ex VAT & shipping) HERON-FPGA12: £1,200
HERON-FPGA12 is supplied without cables as standard. However, some cables can be supplied included in the hardware price, if required. Please specify at time of ordering either up to two FPGA50 or up to two FPGA50-CameraLink-IN cables. See HERON-FPGA12 cables for more information.

The HERON-FPGA12 provides a user programmable element for a HERON system that combines FPGA hardware and a programmable PowerPC^®. The PowerPC^® can be connected as part of the FPGA design allowing users to choose the best mix of hardware and software to perform the signal processing they need.

The module offers 128Mbytes of DDR SDRAM with 1.6Gbyte/sec total memory bandwidth. This off chip memory can be accessed by the PowerPC processor core and also from FPGA logic at the same time (arbitrated). The provided Hardware Interface Layer (HIL) VHDL includes a DDR memory controller that can be connected to user FPGA logic and the PowerPC ODB at the same time.

There is a 16Mbytes FLASH memory connected to the FPGA which is intended for storing boot code for the PowerPC^®. There is a Xilinx provided Core that allows this to be connected to the PowerPC^® directly, but the user can choose to connect their own VHDL to the FLASH memory if their application requires.

The module offers 60 bits of digital I/O, which can have series resistors fitted at build time to allow 5V tolerance. these I/Os can be configured by the FPGA design to use any Virtex-4 format that uses 3.3V Vcco. It should be noted that this means LVDS inputs are an option but not LVDS outputs. 

HERON-FPGA modules must be fitted to a HERON module carrier that provides power and control signals to the module. Most module carriers also offer FIFO based connections between modules and possibly between the modules and a host PC. Normally the configuration program for the FPGA is sent from a host PC via the Heron Serial Bus, allowing fast development, test, debug cycles as well as in-field upgradeability. Alternative ways of configuring the FPGA are the on-board FLASH based configuration PROM, and the JTAG header that accepts standard Xilinx^® JTAG cables such as Xilinx^® Parallel cable 4 or USB-JTAG cable.

After configuration the Heron Serial Bus can be used for inter-module messages allowing FPGA registers to be read and written to control the operation of the module as defined in the FPGA design

The PowerPC^® program can be downloaded as part of the FPGA design, or after the FPGA configuration using the GNU debugger (via the JTAG cable) or the HERON-FIFOs, or can be loaded from the FLASH memory provided on the module.

HERON-FPGA12 Diagram

 

Technical Specification

Xilinx ISE^® tools are required to make a new FPGA configuration.
Xilinx EDK^® tools are required to make new PowerPC configurations.
HUNT ENGINEERING provide software to download the FPGA configuration file onto the hardware, plus configuration examples.
HUNT ENGINEERING may offer to provide your configuration file for you, but this may be chargeable.

Need a ready made function? See the IP available for HERON-FPGA12

  HERON-FPGA12 User Manual 

  Print friendly version of this Datasheet

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