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Tools for Developing FPGA Applications

There are several toolsets which can be used to generate the code for an FPGA. This paper introduces the main options.

The Development Process

The typical development cycle is as follows:

Develop the FPGA VHDL code using one of the toolsets described later. Interface to the hardware using the Hardware Interface Layer provided for your FPGA module – we do not recommend you attempt to modify this!
Logically simulate your FPGA design using Modelsim
Download this FPGA program to the hardware using the Hunt Engineering tools
Debug the FPGA using ChipScope™ tools from Xilinx
Load any DSP code, debug it with Code Composer Studio and test the system.

As can be seen, if your system includes both DSP processor and FPGA we recommend treating development as two separate stages. Develop the FPGA and make sure it’s right; then switch to developing the DSP processor code. This can be done iteratively – develop a basic FPGA, then a basic DSP program, then return to enhance the FPGA code.

The Toolsets

VHDL has become the industry standard method of programming FPGAs. We provide examples and starting projects for our modules written in VHDL. There are several toolsets that support synthesising VHDL for Xilinx FPGAs. We recommend the Xilinx ISE^Ž Foundation tools and have little or no experience of the others; however, the examples have been written in a style that allows the use of third party synthesis tools. The examples have been tested with several other toolsets.

Foundation ISE^Ž

Foundation ISE^Ž is the toolset we use and recommend. It is probably the cheapest option (apart from the limited functionality WebPack^Ž, which is free). It provides all the facilities that you are likely to need.

Designs are entered using VHDL, and the package includes the "core generator". This is an extremely useful utility that can build you a large function block such as an FIR or FFT – leaving you to drop in coefficients and data to get a working system. It also allows you to use other IP cores in your design.

As with other tools, Foundation is continually being extended. Check the Xilinx website for details on the current software release.

WebPack^Ž

WebPack^Ž is a free toolset available from Xilinx's web. It is a limited version of ISE^Ž.

WebPack^Ž only supports a limited range of devices – currently the Spartan-II family and very small Virtex^Ž-IIs (not on any of our modules). If you intend to use an FPGA module with any device other than the Spartan^Ž-II (e.g. Virtex, all Virtex-II) you must buy the ISE^Ž Foundation package.

Designs can still be entered as VHDL . However, the core generator is also not available, so many of the easy examples we show will not work.

We do not recommend the use of WebPack^Ž for signal processing applications. Only use it if you are designing simple logic – like an I/O interface. Also, make sure that the HERON module you are targeting uses an array that is supported by WebPack^Ž.

Other synthesis tools

We have an applications note that discusses using other synthesis tools with the VHDL we supply. We have checked some popular tools like "Synplify" and "Leonardo Spectrum". Ultimately these tools still require some Xilinx software to perform the final Place and Route stage.

System generator

Xilinx provide system generator, that interfaces to the Matlab Simulink^Ž environment. This allows you to use the Matlab "Block Diagram" tools to generate parts of your FPGA design. For more information see the Xilinx web site.

Debugging

Traditionally FPGA designs have been de-bugged with an oscilloscope and probe points that you put in your design routed out to I/Os. The HERON modules allow you to do this if you want, but with the arrival of multi-million gate devices Xilinx realised that something more sophisticated was needed. They provide a tool called ChipScope™ which can be used like a logic analyser for your FPGA design. To do this you compile analysis blocks into your design and connect them to the signals that you want to observe. Using JTAG you can capture the waveforms onto your PC and view them like a logic analyser screen. Most HERON modules support this by providing a JTAG connector where you can connect the Xilinx^Ž JTAG cable (like Xilinx Parallel cable 3 or 4) needed to run ChipScope™.

Summary

Simple - we recommend Foundation. You can extend this with Simulink^Ž if required, but on its own it gives a powerful set of tools for supporting the HERON range.

If you are working on a tight budget and building a very simple system, or have a very in-depth knowledge of the systems you want to create, then WebPack^Ž may be adequate. It is available as a free download, so you can download it and try it – but do not expect all our examples to work, as we use the core generator!